Delay macromodeling and estimation for RTL

We propose a macromodel for delay estimation at the RTL level. The macromodel is useful for approximating the delay through the critical path of an RTL block as a function of V_dd and V_t. It is specifically designed for delay estimation at the early phase of the design flow and based on detailed HSPICE analysis of NAND chains to extract the parameter values. This macromodel has two fitting parameters which make the macromodel simple but accurate. The steps needed to extract the two parameters are described. The validation of the model is demonstrated by comparison with HSPICE. According to our experiments, this macromodel is able to predict the delay variation due to V_dd and V_t with accuracy of plusmn3% at the logic level and plusmn5% for RTL blocks.