Parallel core testing with multiple scan chains by test vector overlapping

This paper proposes the parallel testing of cores with multiple scan chains using the test vector overlapping for reduction of SoC testing cost. Unlike conventional scan architecture for SoC testing, by introducing multiple scan chain cores, our method can reduce the test application time without increasing the number of I/O pins used in testing, and reduce the test data volume. A controller design and a new overlapping algorithm are also presented for the test vector overlapping with multiple scan chain cores. Experimental results show its effectiveness.