Delay defect coverage for FPGA test configurations based on statistical evaluation

Testing for performance problems of FPGAs has become an important task for ever-increasingly advanced technology. To develop effective testing methodologies, a tool to independently evaluate the quality of test configurations is therefore much needed. In this paper, we present a method to calculate coverages of randomly distributed multiple delay defects in FPGAs. The evaluation algorithm can also identify target paths which are not covered in the current configurations, but can contribute to the quality of the tests. It is shown that the reported metrics can be used to quantify the coverage of delay defects and also further improve high-quality test configurations.