Decomposition of instruction decoder for low power designs

During the execution of instructions, instruction decoding is a major task for identifying instruction and generating control signals of data-paths. By tracing program execution sequences, the authors proposed an algorithm that exploits relations between instructions of frequently-executed instruction groups. After partitioning instructions into groups, a two-stage low-power decomposition architecture was used for instruction decoding. Experimental results have demonstrated that the proposed approach achieved an average of 29.97% and 18.94% power reductions, and 12.93% and 12.36% critical-path delay reductions for the instruction decoder and the control unit, respectively.