PA linearization using multi-stage look-up-table predistorter with optimal linear weighted delay

A digital predistortion linearization algorithm using multi-stage look-up-table (LUT) predistorter with optimal linear weighted delay is proposed for memory power amplifiers (PA). In order to find the optimal linear delay weight under the constraint of fewer stages of LUTs which is imposed by the limited hardware resources, minimum normalized mean-square error (MNMSE) is chosen as the criterion. The new algorithm adopts the reference model indirect learning architecture, and updates its LUTs using LMS algorithm without training sequences. The multi-stage LUT predistorter has the simple structure of finite-impulse-response filter, which involves less computational complexity and is easy for hardware implementation. By evaluating optimal linear delay weight, the new algorithm achieves better linearization results. Excellent performance of the new algorithm is validated by results from hardware tests.