DocumentCode
1843069
Title
A wafer scale fail bit analysis system for VLSI memory yield improvement
Author
Sakai, Yuji ; Sawada, Jiro ; Sakamoto, Wataru ; Murato, J. ; Kawamoto, Hiroshi ; Sakai, Kikuo ; Nakamuta, K.
Author_Institution
Hitachi Ltd., Tokyo, Japan
fYear
1990
fDate
5-7 March 1990
Firstpage
175
Lastpage
178
Abstract
A wafer-scale fail bit analysis system which outputs an entire wafer fail bit map (FBM) by using a data compaction technique and testing structure is developed. With this system, process defect locations on a wafer can easily be electrically recognized quickly. The processing time of wafer-scale fail bit analysis is reduced to only 2% of that required by the conventional method. An example of a wafer-scale FBM is shown.<>
Keywords
VLSI; automatic test equipment; data compression; integrated circuit technology; integrated circuit testing; integrated memory circuits; VLSI memory yield improvement; data compaction; process defect locations; processing time; testing structure; wafer fail bit map; wafer scale fail bit analysis system; Circuits; Compaction; Data engineering; Data processing; Displays; Failure analysis; Flowcharts; Solids; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on
Conference_Location
San Diego, CA, USA
Type
conf
DOI
10.1109/ICMTS.1990.67899
Filename
67899
Link To Document