DocumentCode
1843524
Title
Expression and verification of temporal constraints for real-time systems
Author
Delfieu, D. ; Sahraoui, A.E.K.
Author_Institution
Lab. d´´Autom. et d´´Analyse des Syst., CNRS, Toulouse, France
fYear
1993
fDate
24-27 May 1993
Firstpage
383
Lastpage
391
Abstract
A preliminary approach to deal with timing constraints is given. It is shown how to analyze the notion of temporal constraints, and a simple way to express them using the notion of language is proposed. To test the temporal aspects of a full verification, an execution trace on the acceptor of the language is checked. This allows testing of a full specification expressed in any formalism
Keywords
formal specification; formal verification; real-time systems; execution trace; full verification; real-time systems; temporal constraints; timing constraints; Boolean functions; Control systems; Embedded system; Logic; Radar; Real time systems; Robustness; Safety; Terminology; User interfaces;
fLanguage
English
Publisher
ieee
Conference_Titel
CompEuro '93. 'Computers in Design, Manufacturing, and Production', Proceedings.
Conference_Location
Pris-Evry
Print_ISBN
0-8186-4030-8
Type
conf
DOI
10.1109/CMPEUR.1993.289849
Filename
289849
Link To Document