Don’t care filling for power minimization in VLSI circuit testing

Power minimization is one of the very important issues in the testing of power constrained VLSI circuit. While existing literature emphasizes dynamic power reduction, leakage power is assuming more and more importance in the forthcoming technologies beyond 100 nm. This paper studies the effect of don´t care filling of the patterns generated via automated test pattern generators, to make the patterns consume lesser power. It presents a trade-off in the dynamic and static power consumption. Judicious selection of don´t cares can provide a trade-off of 17% dynamic power. For static power the trade-off is about 2.4% in the 0.18 mum technology. The effect is expected to be more prominent for technologies beyond 100 nm.