TLM: a trench leakage monitor for a four megabit DRAM technology

Author

Voldman, Steven H. ; Long, Christopher W.

Author_Institution

IBM Gen. Technol. Div., Essex Junction, VT, USA

fYear

1990

fDate

5-7 March 1990

Firstpage

237

Lastpage

241

Abstract

An array of substrate-plate trench-capacitor dynamic random access memory (DRAM) cells is used for quantification of parasitic leakage mechanisms, silicon defects, and device parametrics. Parasitic devices aid process characterization, parametric cross-correlations, and technology/device design-point evaluation. Used in conjunction with a functional monitor, the trench leakage monitor, is found to be a valuable semiconductor process-development vehicle to achieve functionality and cell-retention yield for a 4-Mb DRAM CMOS technology.<>

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated circuit testing; integrated memory circuits; random-access storage; 4 Mbit; CMOS; DRAM; Si defects; TLM; cell-retention yield; device parametrics; dynamic random access memory; functional monitor; parametric cross-correlations; parasitic devices; process characterization; quantification of parasitic leakage mechanisms; semiconductor process-development vehicle; substrate-plate trench-capacitor; technology/device design-point evaluation; test structures; trench leakage monitor; CMOS technology; Capacitors; Implants; Isolation technology; Monitoring; Parasitic capacitance; Random access memory; Substrates; Testing; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/ICMTS.1990.67910

Filename

67910