• DocumentCode
    1845086
  • Title

    Delay independent initialization of sequential circuits

  • Author

    Chakraborty, Tapan J. ; Agrawal, Vishwani D.

  • Author_Institution
    AT&T Bell Labs., Princeton, NJ, USA
  • fYear
    1994
  • fDate
    4-5 Mar 1994
  • Firstpage
    228
  • Lastpage
    230
  • Abstract
    We show that a given initialization sequence for a synchronous sequential circuit is not guaranteed to work correctly when arbitrary path delays are present in the circuit. In this paper, we present a novel robust-initialization procedure for sequential circuits. This procedure guarantees the correct initialization of state elements of a sequential circuit regardless of delays in the circuit. Every pattern of the normal initialization sequence is repeatedly clocked in flip-flops, so that excessive delays on combinational paths feeding flip-flops do not prevent the proper initialization. This method guarantees the correct initialization of pipeline circuits. For a general sequential circuit which may have feedbacks, we give a simulation procedure to determine the initial state of the circuit that is guaranteed to be correct for arbitrarily large but bounded delays
  • Keywords
    circuit analysis computing; flip-flops; logic CAD; logic testing; pipeline processing; sequential circuits; delay independent initialization; feedback; flip-flops; path delays; pipeline circuits; robust-initialization procedure; simulation algorithm; synchronous sequential circuit; Circuit faults; Circuit simulation; Circuit testing; Clocks; Delay; Logic circuits; Logic design; Logic testing; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on
  • Conference_Location
    Notre Dame, IN
  • Print_ISBN
    0-8186-5610-7
  • Type

    conf

  • DOI
    10.1109/GLSV.1994.289964
  • Filename
    289964