An algorithm-base fault tolerance (more than one error) using concurrent error detection for FFT processors

Author

Sha, Chin-Chicn ; Leavene, R.W.

Author_Institution

Dept. of Electr. & Comput. Eng., Missouri Univ., Columbia, MO, USA

fYear

1994

fDate

4-5 Mar 1994

Firstpage

56

Lastpage

61

Abstract

An algorithm is proposed to maintain fault tolerance for a highly reliable FFT processor, even after the processor has been reconfigured (by detecting a single fault). It proves that the concurrent error detection (CED) scheme using: a redundant stage of decimation in frequency FFT (DIF-FFT) butterflies as a decoder can detect all the faults theoretically. This CED scheme and the modification of the standard DIF-FFT processor as a recirculated shuffle exchange will also alleviate the difficulty of reconfiguration and will provide the ability of some degradation in performance in the presence of more than one fault in the processor

Keywords

circuit reliability; digital arithmetic; error detection; fast Fourier transforms; fault tolerant computing; multiprocessor interconnection networks; pipeline processing; FFT processors; algorithm-base fault tolerance; concurrent error detection; decimation in frequency FFT butterflies; decoder; discrete Fourier transform; multi error fault tolerance; pipeline processor; processor reconfiguration; recirculated shuffle exchange; Decoding; Discrete Fourier transforms; Fast Fourier transforms; Fault detection; Fault tolerance; Fourier transforms; Hardware;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on

Conference_Location

Notre Dame, IN

Print_ISBN

0-8186-5610-7

Type

conf

DOI

10.1109/GLSV.1994.289995

Filename

289995