Heterogeneous systems verification on HiLeS Designer tool

Verification is one of the most important tasks into the process of systems design. This time-consuming task guarantees the correct functionality of the system. We propose to use HiLeS Designer tool to model and to verify heterogeneous systems in order to reduce functionality risks and time. This tool allows verifying in two ways: formal verification on the model logical sequence and verification by simulation where a virtual prototype on VHDL-AMS is generated from the model. A cane sugar production process is presented as illustrative example.