Modified CSD group multiplier design for predetermined coefficient groups

Some digital signal processing applications, such as FFT, request multiplications with a group (or, groups) of a few predetermined coefficients. In this paper, based on a grouping method of CSD coefficients, an efficient multiplier design method for predetermined coefficient groups is proposed. In the case of the multiplier design for sine-cosine generator used in direct digital frequency synthesizer(DDFS), it is shown that by the proposed method, area, power and delay time can be reduced by 53.1%, 45.6% and 22.6%, respectively, compared with conventional design. Also, in the case of multiplier design used in 128 point radix-24 FFT, the area, power and delay time can be reduced by 42.9%, 58.5% and 19.7%, respectively.