A hybrid self-testing methodology of processor cores

Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new SBST methodology that uses information abstracted from the processor instruction set architecture (ISA), pipeline architecture model, RTL descriptions, and gate-level net-list for test program development of different types of the processor circuitry. This paper demonstrates the feasibility of the proposed methodology by the achieved fault coverage on a complex pipeline processor core. Comparisons with previous work are also made. Experimental results show its potential as an effective method for practical use.