DocumentCode
1849993
Title
Fast carry free adder design using QSD number system
Author
Awwal, A.A.S. ; Ahmed, J.U.
Author_Institution
Dept. of Comput. Sci. & Eng., Wright State Univ., Dayton, OH, USA
fYear
1993
fDate
24-28 May 1993
Firstpage
1085
Abstract
A high speed parallel full adder is designed which can perform carry-free addition of two modified signed digit quaternary numbers. For digital implementation, the sign digit quaternary numbers are represented using 3-bit 2´s complement notation. The adder truth table with possible schemes of the electronic and optical implementation are provided
Keywords
adders; combinatorial circuits; digital arithmetic; encoding; logic design; optical information processing; parallel processing; QSD number system; carry free adder design; digital implementation; electronic implementation; high speed parallel full adder; modified signed digit quaternary numbers; optical implementation; truth table; Adders; Circuits; Computer science; Design engineering; Digital arithmetic; High speed optical techniques; Logic devices; Optical computing; Optical propagation; Programmable logic devices;
fLanguage
English
Publisher
ieee
Conference_Titel
Aerospace and Electronics Conference, 1993. NAECON 1993., Proceedings of the IEEE 1993 National
Conference_Location
Dayton, OH
Print_ISBN
0-7803-1295-3
Type
conf
DOI
10.1109/NAECON.1993.290791
Filename
290791
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