Macro-modeling concepts for the chip electrical interface

The power delivery network is made up of passive elements in the distribution network, as well as the active transistor loads. A chip typically has three types of power supplies that require attention: core, I/O, and analog. Core circuits consist of digital circuits and have the largest current demand. In addition to all of the system issues/models for the core, modeling the I/O subsystem has the additional requirement of modeling return paths and discontinuities. The analog circuits present yet a different challenge to the macromodeling of the supply network because they place a tight demand on supply variations. This paper presents a design methodology on how to generate macro-models of the entire chip electrical interface. This methodology can be used by the chip, package, and system designers and is being used to design high-reliability servers.