Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter

Author

Vandenbussche, J. ; Uyttenhove, K. ; Lauwers, E. ; Steyaert, M. ; Gielen, G.

Author_Institution

Dept. of Electr. Eng., Katholieke Univ., Leuven, Heverlee, Belgium

fYear

2002

fDate

2002

Firstpage

449

Lastpage

454

Abstract

The systematic design of a high-speed, high-accuracy Nyquist-rate A/D converter is proposed. The presented design methodology covers the complete flow and is supported by software tools. A generic behavioral model is used to explore the A/D converter´s specifications during high-level design and exploration. The inputs to the flow are the specifications of the AID converter and the technology process. The result is a generated layout and the corresponding extracted behavioral model. The approach has been applied to a real-life test case, where a Nyquist-rate 8-bit 200 MS/s 4-2 interpolating/averaging A/D converter was developed for a WLAN application.

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit CAD; circuit optimisation; integrated circuit design; integrated circuit layout; interpolation; simulated annealing; 0.35 micron; 2.5 V; 200 MS/s 8-bit interpolating/averaging A/D converter; 3.3 V; 8 bit; CMOS process; WLAN application; design methodology; extracted behavioral model; generated layout; generic behavioral model; global optimization; high-level design; high-speed high-accuracy Nyquist-rate A/D converter; simulated annealing; software tools; systematic design; Circuit simulation; Circuit testing; Design methodology; Error correction codes; Hardware design languages; Permission; Preamplifiers; Simulated annealing; Software tools; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2002. Proceedings. 39th

ISSN

0738-100X

Print_ISBN

1-58113-461-4

Type

conf

DOI

10.1109/DAC.2002.1012667

Filename

1012667