Petri net modeling of gate and interconnect delays for power estimation

Author

Murugavel, Ashok K. ; Ranganathan, N.

Author_Institution

Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA

fYear

2002

fDate

2002

Firstpage

455

Lastpage

460

Abstract

In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net (HCHPN), to model real-delay switching activity for power estimation is proposed. A logic circuit is converted into an HCHPN and simulated as a Petri net to obtain the switching activity estimate and thus the power values. The method is accurate and is significantly faster than other simulation methods. The HCHPN yields an average error of 4.9% with respect to Hspice for ISCAS ´85 benchmark circuits. The per-pattern simulation time is about 46 times less than PowerMill.

Keywords

CMOS logic circuits; Petri nets; circuit simulation; delay estimation; integrated circuit interconnections; integrated circuit modelling; logic simulation; low-power electronics; ISCAS 85 benchmark circuits; MOSIS standard cell CMOS technology; Petri net modeling; deep sub-micron ICs; gate delays; hierarchical colored hardware Petri net; interconnect delays; logic circuit; per-pattern simulation time; power estimation; real-delay switching activity; switching activity; Circuit simulation; Delay effects; Delay estimation; Discrete event simulation; Hardware; Integrated circuit interconnections; Logic circuits; Microelectronics; Permission; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2002. Proceedings. 39th

ISSN

0738-100X

Print_ISBN

1-58113-461-4

Type

conf

DOI

10.1109/DAC.2002.1012668

Filename

1012668