• DocumentCode
    1853777
  • Title

    A 10-bit 300MHz 0.1mm2 triple-channel current-steering DAC 75.98dB SFDR in 65nm

  • Author

    Hong, G.M. ; Hsu, Shih-Hsuan ; Peng, Yan-Hua ; Chen, Alvin Hsin-Hung ; Wang, Yi-Ti ; Lu, Hsin-Hung

  • Author_Institution
    Infrastruct. Res. Dev. Center, Faraday Technol. Corp., Hsinchu
  • fYear
    2008
  • fDate
    23-25 April 2008
  • Firstpage
    148
  • Lastpage
    151
  • Abstract
    For this paper, we used the UMC 65 nm 1P10M CMOS logic process to design a 10-bit triple-channel current- steering DAC, which includes three channels of RGB. The analog/digital circuit was 2.5 V/1.2 V, the active area was 0.1 mm2 per channel, and INL/DNL were each less than plusmn 0.4/plusmn 0.23LSB. We obtained an SFDR exceeding 75.98 dB while consuming only 6.24 mW of power per channel.
  • Keywords
    CMOS logic circuits; digital-analogue conversion; integrated circuit design; DAC design; UMC 65 nm 1P10M CMOS logic process; frequency 300 MHz; size 65 nm; triple-channel current-steering DAC; voltage 1.2 V; voltage 2.5 V; word length 10 bit; Binary codes; CMOS logic circuits; CMOS process; Clocks; Digital circuits; Logic design; Photonic band gap; Sampling methods; Virtual colonoscopy; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on
  • Conference_Location
    Hsinchu
  • Print_ISBN
    978-1-4244-1616-5
  • Electronic_ISBN
    978-1-4244-1617-2
  • Type

    conf

  • DOI
    10.1109/VDAT.2008.4542434
  • Filename
    4542434
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1853777