A single-chip MPEG-2 codec based on customizable media microprocessor

Author

Ishiwata, Shunichi ; Yamakage, Tomoo ; Tsuboi, Yoshiro ; Shimazawa, Takayoshi ; Kitazawa, Tomoko ; Michinaka, Shuji ; Yahagi, Kunihiko ; Takeda, Hideki ; Oue, Akihiro ; Kodama, Tomoya ; Matsumoto, Nobu ; Kamei, Takayuki ; Miyamori, Takashi ; Ootomo, Goich

Author_Institution

Syst. LSI Res. & Dev. Center, Toshiba Corp., Kanagawa, Japan

fYear

2002

fDate

2002

Firstpage

163

Lastpage

166

Abstract

A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on a 72mm² die, is described. It has a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video, audio etc. concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a VLIW one and a DSP one inherent in its architecture. Making full use of the extensions, the chip executes encoding and decoding of video, audio and system concurrently in real time.

Keywords

CMOS digital integrated circuits; application specific integrated circuits; audio coding; code standards; codecs; data compression; microprocessor chips; multimedia communication; parallel architectures; real-time systems; reduced instruction set computing; video coding; CMOS technology; DSP extension; MPEG2 MP@ML codec; RISC core; VLIW extension; application specific signal processor; audio; customizable media microprocessor; decoding; digital media processing; encoding; heterogeneous multiprocessor architecture; instruction set; single-chip MPEG-2 codec; video; Codecs; Decoding; Digital signal processing; Digital signal processing chips; Hardware; Microprocessors; Read-write memory; Reduced instruction set computing; Research and development; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002

Print_ISBN

0-7803-7250-6

Type

conf

DOI

10.1109/CICC.2002.1012789

Filename

1012789