Parallel design for parallel decision feedback decoders for 10GBASE-T

10GBASE-T (10 Gigabit Ethernet over unshielded twisted pairs) will probably use a 10-level pulse amplitude modulation (PAM10) as well as a 4D trellis code as in 1000BASE-T (1000 Megabit Ethernet over copper medium). One of most powerful approaches to decode the code is called parallel decision-feedback decoding. However, VLSI implementation of a PDFD (parallel decision-feedback decoder) operating at 833 MHz is extremely challenging due to its long critical path. This paper extends the word-level parallel processing technique for Viterbi decoders to design high speed parallel PDFDs. Compared with the straight-forward implementation of PDFDs, a 2-level parallel PDFD can achieve a speedup of 1.5 while the speedup for a 3-level parallel PDFD is around 2. More speedup is achievable if we combine some other techniques, such as pre-computation technique.