Logic-enhanced memory for 3D graphics tile-based rasterizers

An efficient logic-enhanced memory architecture to accelerate primitive traversal in 3D graphics tile-based rasterizers is presented. The memory contains the same number of bits as the number of pixels in the tile, and during rasterization time it is filled up in several clock cycles by a systolic primitive scan-conversion subsystem with the stencil of the primitive: ones are written for memory locations that represent tile pixels covered by primitive, otherwise zeros are stored. The logic-enhanced memory architecture presents the following benefits: it handles "ghost" primitives efficiently, hit positions are communicated in a spatial pattern that increases the hit ratio of texture caches in pull texture architectures, and hit positions can always be mapped to different memory banks in the Z-buffer or color-buffer breaking the "read-modify-write" dependency associated with depth test and color blending thus allowing efficient pipelining. Hardware implementation in a typical 0.18μm process technology for a QVGA 3D graphics hardware accelerator with a tile size of 32×16 pixels has indicated that the memory can be clocked at 200 MHz and consumes an area of 120000 μm².