Energy macro-modeling of embedded microprocessor using SystemC

System-on-chip (SoC) is increasingly adopted in VLSI world with the advancing silicon technologies. Integrating multiple functional IPs (intellectual property) onto a single die increases performance and saves power consumption by reducing interconnecting capacitance among these IPs. Embedded microprocessor acts as the central controlling unit of many SoCs to orchestrate all the other IPs to work harmoniously. Low and predictable energy consumption is often required for these systems. This paper proposes an empirical macro-modeling methodology allowing energy modeling at the system level. High-level macro-operations are characterized for energy consumption. This modeling framework is implemented for a MIPS-family microprocessor using SystemC, a system-level modeling and simulation environment. Using the JPEG encoder application as case study, a simulation speed-up of more than 200 times with the relative error of -6.70% on energy estimation is achieved compared to instruction-level simulators. Meanwhile, this model provides support to multiprocessor energy modeling, which is unavailable currently in the instruction-level energy simulators