DocumentCode
1857304
Title
Package to board interconnect design for minimum return loss
Author
Sanchez, Adan S. ; Romo, Gerardo ; Armenta, Luis F.
Author_Institution
Syst. Res. Center, Mexico Intel, Tlaquepaque
fYear
2008
fDate
28-30 April 2008
Firstpage
1
Lastpage
4
Abstract
Return loss from impedance discontinuities severely limits the bandwidth and power efficiency of chip-to-chip copper interconnects. Among the more frequently found discontinuities are vertical transitions connecting signals in different layers in the system. In this work, we present a general condition to improve return loss in vertical package to board transitions in high speed links. The relationship involves the impedance of on-package and on-board transmission lines as well as the via model. Experimental results that apply the proposed method show a 10-dB improvement in return loss. The proposed method can be applied in the design of copper interconnects with minimum reflection, which is a requirement of high-speed and low-power signaling systems.
Keywords
chip-on-board packaging; copper; electric impedance; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; chip-to-chip copper interconnects; on-board transmission lines; on-package transmission lines; package-to-board interconnect design; return loss; Bandwidth; Copper; Impedance; Joining processes; Packaging; Power system interconnection; Power transmission lines; Reflection; Signal design; Transmission line discontinuities;
fLanguage
English
Publisher
ieee
Conference_Titel
Devices, Circuits and Systems, 2008. ICCDCS 2008. 7th International Caribbean Conference on
Conference_Location
Cancun
Print_ISBN
978-1-4244-1956-2
Electronic_ISBN
978-1-4244-1957-9
Type
conf
DOI
10.1109/ICCDCS.2008.4542608
Filename
4542608
Link To Document