Pipelined operation of image capturing and processing

This paper presents an Field Programmable gate Array (FPGA) integrated architecture to perform a pipelined operations of image capturing, convolution and sorting, which are usually done serially. When pixels serially coming from image sensor pile up a first n×n window, a convolution with selected coefficient of n×n matrix can be started to obtain a target image pixel. After the target image pixels pile up another n×n window again. Maheshwari sorting is performed and three values (max, mid, min) are obtained simultaneously, ready for next processing. Convolution and sorting help further filtering image noises, such as dark current noise and Fixed Pattern Noise (FPN) in CMOS image sensor. This is one of the main reasons that make the FPGA integrated image processing device demonstrate a higher image qualities. A faster capturing speed is also gained due to using hardware-oriented FPGA instead of ordinary software-programmed 8051 series microprocessor.