Leading Edge Technology and Test Noise

Author

Takayuki, Katayama ; Ebihara, Kou ; Imaizumi, Goro

Author_Institution

Fujitsu Microelectron. Ltd.

fYear

2008

fDate

24-27 Nov. 2008

Firstpage

269

Lastpage

269

Abstract

The power consumption under test is paid to attention in recent years especially in advanced technology node. It is often reported that there are deep relation between the yield loss and power integrity, which is critical to circuit operation at testing. This is because structural test operates even more circuits than usual system operation.This issue will also be more critical according to process technology evolution. In this report, the amount of the noise at memory built-in self-test (BIST) and transition delay test (TDT) which are major method of structural test is observed. And its influence on device is considered.

Keywords

built-in self test; integrated circuit noise; integrated circuit testing; large scale integration; low-power electronics; power electronics; BIST; LSI; built-in self-test; power consumption; power integrity; power supply noise; process technology; structural test noise; transition delay test; yield loss; Built-in self-test; Circuit noise; Circuit testing; Delay; Energy consumption; Noise reduction; Power supplies; System testing; Voltage; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Asian Test Symposium, 2008. ATS '08. 17th

Conference_Location

Sapporo

ISSN

1081-7735

Print_ISBN

978-0-7695-3396-4

Type

conf

DOI

10.1109/ATS.2008.85

Filename

4711600