Reliable router architecture with elastic buffer for NoC architecture

Router is the basic building block of the interconnection network. In this paper, new router architecture with elastic buffer is proposed which is reliable and also has less area and power consumption. The proposed router architecture is based on new error detection mechanisms appropriate for dynamic NoC architectures. It considers data packet error detection, correction and also routing errors. The uniqueness of the reliable router architecture is to focus on finding error sources accurately. This technique differentiates permanent and transient errors and also protects diagonal availabilities. Input and output buffers in router architectures are replaced by elastic buffers. Routers spend considerable area and power for router buffer. In this paper the proposed router architecture replaces FIFO buffers with the elastic buffers in order to reduce area, and power consumption and also to have better performance.