• DocumentCode
    1858842
  • Title

    PC-Mesh: A Dynamic Parallel Concentrated Mesh

  • Author

    Camacho, J. ; Flich, J. ; Roca, A. ; Duato, J.

  • Author_Institution
    Parallel Archit. Group, Univ. Politec. de Valencia, Valencia, Spain
  • fYear
    2011
  • fDate
    13-16 Sept. 2011
  • Firstpage
    642
  • Lastpage
    651
  • Abstract
    We present a novel network on-chip topology, PC-Mesh (Parallel Concentrated Mesh), suitable for tiled CMP systems. The topology is built using four concentrated mesh (C-Mesh) networks and a new network interface able to inject packets through different networks. The goal of the new combined topology is to minimize the power consumption of the network when running applications exhibiting low traffic rates and maximize throughput when applications require high traffic rates. Thus, the topology is dynamically adjusted (switching on and off network components) with a proper injection algorithm, adapting itself to the network on-chip traffic requirements. The PC-Mesh network performs as a C-Mesh network (using one sub network) when the traffic is low obtaining large savings in power consumption. When the load network increases, new sub networks are opened and thus higher traffic rates are supported, thus providing comparable results as the mesh network. Additional benefits of the PC-Mesh network is its fault tolerance degree and the lower latency in terms of hops. An alternative PC-Mesh version is provided to optimize the fault-tolerance degree. Comparative results with detailed evaluations (in area, power, and delay) are provided both for the network interface and switches. Results demonstrate PC-Mesh is able to dynamically adapt to the current traffic situations. Experimental results with a system-level simulation platform (including the application being run and the operating system) are provided. Results show how the PC-Mesh network achieves the same results as the C-Mesh topology reducing execution time of applications by 20% as well as energy consumption by also 20%, when compared with the 2D-Mesh network topology. However, when challenged with higher traffic demands, PC-Mesh outperforms the C-Mesh network by achieving much lower execution time of applications and lower energy consumption. In some scenarios, execution time is reduced by a factor of 2 and power cons- - umption by 50%.
  • Keywords
    fault tolerance; multiprocessing systems; network-on-chip; telecommunication network topology; 2D-Mesh network topology; C-Mesh topology; PC-Mesh network; dynamic parallel concentrated mesh; energy consumption; fault tolerance degree; network interface; network-on-chip topology; network-on-chip traffic requirements; power consumption; system-level simulation platform; tiled CMP system; Algorithm design and analysis; Fault tolerance; Fault tolerant systems; Network topology; Power demand; Switches; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing (ICPP), 2011 International Conference on
  • Conference_Location
    Taipei City
  • ISSN
    0190-3918
  • Print_ISBN
    978-1-4577-1336-1
  • Electronic_ISBN
    0190-3918
  • Type

    conf

  • DOI
    10.1109/ICPP.2011.21
  • Filename
    6047232