Design Space Exploration of RISC Architectures using retargetability

Processor development is done in stages. It is a safe bet if we start by modeling the processor at a high level of abstraction, perform refinements at high level, and when we are satisfied by the performance, go into manufacturing. The process of refinement is done by evaluating the design criteria. This process generally goes through a cycle that can be described as Design Space Exploration (DSE). In this paper, we describe how to model a processor in an Architecture Description Language (ADL), how to generate tools to perform DSE, and finally how to evaluate performance.