DocumentCode
1859583
Title
An approach to implement FIR filters for delta sigma inputs
Author
Babaii, Nikzad ; Nabavi, Abdolreza
Author_Institution
Dept. of Electr. Eng., Tarbiat Modares Umversity, Tehran, Iran
Volume
2
fYear
2002
fDate
2002
Firstpage
1040
Abstract
In this paper, a new structure to implement FIR delta sigma filters is presented. In this structure top data-coefficient multiplications are placed in multiple separate memory blocks then the outputs of the memory blocks are added together which results in the final output. By choosing the number of memory blocks, we can control the number of used gates, and the delay.
Keywords
FIR filters; delays; digital filters; FIR filters; data-coefficient multiplications; delay control; delta sigma filters; memory block outputs; multiple separate memory blocks; used gates; Added delay; Adders; Algorithm design and analysis; Data engineering; Digital filters; Digital signal processing; Filtering algorithms; Finite impulse response filter; Hardware; Mercury (metals);
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 2002. IEEE CCECE 2002. Canadian Conference on
ISSN
0840-7789
Print_ISBN
0-7803-7514-9
Type
conf
DOI
10.1109/CCECE.2002.1013088
Filename
1013088
Link To Document