Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components

Author

Zhang, Zhen ; Greiner, Alain ; Benabdenbi, Mounir

Author_Institution

LIP6-SoC Lab., Univ. Pierre et Marie Curie, Paris, France

fYear

2010

fDate

5-7 July 2010

Firstpage

194

Lastpage

196

Abstract

In this paper, we present an embedded, at speed, off-line, and fully distributed initialization procedure for 2D-Mesh Network-on-Chip (NoC). This procedure is executed at power boot, and targets the detection and the deactivation of the faulty routers and/or faulty communication channels. The final objective is fault tolerance. The proposed procedure is able to clean the NoC from all destructive malfunctions induced by permanent hardware failures. This initialization procedure has been implemented in a reconfigurable version of the DSPIN micro-network, and evaluated from the point of view of Stuck-at fault coverage, and area overhead.

Keywords

built-in self test; fault tolerance; network-on-chip; 2D-mesh NoC; DSPIN micronetwork; area overhead; fault tolerance; faulty communication channels; faulty components; faulty routers; fully distributed initialization procedure; network-on-chip; off-line BIST; partial deactivation; permanent hardware failures; stuck-at fault coverage; Built-in self-test; Clocks; Communication channels; Fault tolerance; Fault tolerant systems; Laboratories; Multiplexing;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International

Conference_Location

Corfu

Print_ISBN

978-1-4244-7724-1

Type

conf

DOI

10.1109/IOLTS.2010.5560209

Filename

5560209