A bit level area aware cache-based architecture for memory repairs

In this paper an architecture for memory Built-In Self-Repair (BISR) is presented. The proposed scheme utilises a multiple bank cache-like memory for repairing defective bits and is a heavily modified version of a previously studied architecture that repaired at the word level, while the proposed repairs at the bit level. This scheme achieves high repair ratios at high defect densities with small overheads. The two architectures are compared on their footprint by means of an area approximation analysis. The proposed modified scheme shows significant area savings (greater than 4 times) while retaining the same high repairability qualities as its predecessor.