• DocumentCode
    1860477
  • Title

    Recomposing an Irregular Algorithm Using a Novel Low-Level PGAS Model

  • Author

    Cason, Megan ; Kogge, Peter M.

  • Author_Institution
    Inf. Technol. Lab., US Army Corps of Eng., Vicksburg, MS, USA
  • fYear
    2011
  • fDate
    13-16 Sept. 2011
  • Firstpage
    238
  • Lastpage
    248
  • Abstract
    This paper presents analysis and simulation results for a toolkit of parallel graph traversal primitives which were built using a novel, low-level partitioned global address space (PGAS) programming model. Unlike high-level HEC PGAS languages (UPC, Chapel, Fortress), this mobile-subjective (MoS) model does not hide parallelization or communication overhead in the compiler or runtime. Unlike other low-level HEC languages (C/MPI) this model provides 1) facilities for fine-grain synchronization, 2) PGAS view of memory, and 3) object encapsulation. This paper shows how this programming model facilitated the transformation of the well-studied minimum spanning forest (MSF) algorithm into a new MSF algorithm which allowed for million way well-behaved parallelism on a novel multithreaded architecture. We provide analysis to show why naive formulations of MSF are not scalable for certain input graphs. We then provide analysis of the MoS reformulation to show how scalability is achieved by ensuring a good distribution of data and computation for arbitrary input graphs.
  • Keywords
    data encapsulation; mobile computing; multi-threading; trees (mathematics); MSF algorithm; communication overhead; data distribution; fine grain synchronization; low-level PGAS model; low-level partitioned global address space programming model; minimum spanning forest algorithm; mobile subjective model; multithreaded architecture; object encapsulation; parallel graph traversal primitives; parallelization; programming model; Algorithm design and analysis; Electronics packaging; Parallel processing; Partitioning algorithms; Programming; Scalability; Synchronization; graph traversal; multithreaded architecture; parallel programming models;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing Workshops (ICPPW), 2011 40th International Conference on
  • Conference_Location
    Taipei City
  • ISSN
    1530-2016
  • Print_ISBN
    978-1-4577-1337-8
  • Electronic_ISBN
    1530-2016
  • Type

    conf

  • DOI
    10.1109/ICPPW.2011.55
  • Filename
    6047298