• DocumentCode
    1861881
  • Title

    A 100MHz ladder FeRAM design with capacitance-coupled-bitline (CCB) cell

  • Author

    Takashima, Daisaburo ; Nagadomi, Yasushi ; Ozaki, Tohru

  • Author_Institution
    Center for Semicond. R&D, Toshiba Corp., Yokohama, Japan
  • fYear
    2010
  • fDate
    16-18 June 2010
  • Firstpage
    227
  • Lastpage
    228
  • Abstract
    This paper presents fast 10-ns read/write cycle FeRAM with small 0.35μm2 cell using highly reliable large ferroelectric capacitor of 0.145μm2 and with highly compatible process with logic-LSI.
  • Keywords
    ferroelectric capacitors; large scale integration; logic circuits; random-access storage; CCB cell; capacitance-coupled-bitline cell; ferroelectric capacitor; ladder FeRAM design; logic-LSI; read/write cycle FeRAM; Arrays; Capacitors; Ferroelectric films; Microprocessors; Nonvolatile memory; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2010 IEEE Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-5454-9
  • Type

    conf

  • DOI
    10.1109/VLSIC.2010.5560289
  • Filename
    5560289
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1861881