Power supply noise reduction using additional resistors

Author

Rauscher, Jürgen ; Pfleiderer, Hans-Jörg

Author_Institution

Dept. of Microelectron., Ulm Univ., Germany

fYear

2005

fDate

10-13 May 2005

Firstpage

193

Lastpage

196

Abstract

For high performance chips power noise issues become more prominent. In this paper power supply noise is damped with additional resistors in the impedance path between the package and the on-chip power distribution. Therefore, this path is split into several paths with different resistors. A distributed 2D signal line on-chip model in a simulated annealing schedule is utilized to find the appropriate resistors. The amount of noise reduction and the necessary voltage offset to overcome the additional IR drop has been investigated in several simulations. Further, the influence of splitting the power supply path only into very few different paths has been investigated.

Keywords

circuit optimisation; integrated circuit noise; power supply circuits; resistors; simulated annealing; distributed 2D signal line on-chip model; high performance chips; on-chip power distribution; power supply noise reduction; resistors; simulated annealing; voltage offset; Admittance; Capacitance; Damping; Noise reduction; Packaging; Power distribution; Power supplies; Resistors; Simulated annealing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Propagation on Interconnects, 2005. Proceedings. 9th IEEE Workshop on

Print_ISBN

0-7803-9054-7

Type

conf

DOI

10.1109/SPI.2005.1500942

Filename

1500942