Design and simulation of high frame frequency CMOS camera image acquisition system

For the requirement of high frame in supervision and control for instruments in compartment and record of missiles lunching outside the compartment of a fighter, a high frame CMOS image acquisition system based on the FPGA is designed. High speed CMOS image sensor LUPA-300 is used in this system. Xilinx´s FPGA is used as timing and readout of the image sensor and image transmission controlling. FIFO generated by FPGA using Verilog HDL (Hardware Description Language) achieves high-speed image data buffering. Camera Link interface is used to communicate with the image acquisition card of the host computer. The Experiments of the system show the frame can reach 249.6 fps in a format of 640 * 480 with the clock of 80 MHz.