DocumentCode
1866134
Title
Shifted Recursive Torus interconnection for high performance computing
Author
Inoguchi, Yasushi ; Horiguchi, Susumu
Author_Institution
Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
fYear
1997
fDate
28 Apr-2 May 1997
Firstpage
61
Lastpage
66
Abstract
We propose the Shifted Recursive Torus (SRT) interconnection network for high performance computing. By adding multi level links to the torus network recursively, the SRT can achieve excellent interconnection features such as a smaller diameter, a limited number of links per node, an easy implementation in VLSI, and an expandible hierarchical structure. The paper considers the problem of achieving an efficient routing on the SRT. It proposes a recursive routing algorithm on the SRT whose performance is almost the same as optimal routing. A high performance computing of FFT is discussed by embedding the data structure into the SRT
Keywords
fast Fourier transforms; multiprocessor interconnection networks; parallel algorithms; parallel architectures; FFT; SRT; Shifted Recursive Torus interconnection network; data structure; expandible hierarchical structure; high performance computing; interconnection features; multi level links; recursive routing algorithm; torus network; Broadcasting; Computer networks; Data structures; Embedded computing; High performance computing; Multiprocessing systems; Multiprocessor interconnection networks; Routing; Very large scale integration; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing on the Information Superhighway, 1997. HPC Asia '97
Conference_Location
Seoul
Print_ISBN
0-8186-7901-8
Type
conf
DOI
10.1109/HPC.1997.592123
Filename
592123
Link To Document