A 0.18 /spl mu/m logic-based MRAM technology for high performance nonvolatile memory applications

Author

Sitaram, A.R. ; Abraham, D.W. ; Alof, C. ; Braun, D. ; Brown, S. ; Costrini, G. ; Findeis, F. ; Gaidis, M. ; Galligan, E. ; Glashauser, W. ; Gupta, A. ; Hoenigschmid, H. ; Hummel, J. ; Kanakasabapathy, S. ; Kasko, I. ; Kim, W. ; Klostermann, U. ; Lee, G.Y

Author_Institution

MRAM Dev. Alliance, Infineon Technol., Hopewell Junction, NY, USA

fYear

2003

fDate

10-12 June 2003

Firstpage

15

Lastpage

16

Abstract

This paper discusses the fabrication of a 2 Kb array test chip with a 1.66 /spl mu/m/sup 2/ cell and a corresponding 128 Kb MRAM (Magnetoresistive Random Access Memory) with a 1.4 /spl mu/m/sup 2/ cell. The technology features a 1 transistor 1 MTJ (Magnetic Tunnel Junction) cell in a 0.18 /spl mu/m, 3 level Cu metallization logic-based process. Outlined here is a yield analysis of the read operation, which is governed by the MTJ resistance distribution function and a systematic study of the write operation. MRAM functionality, with a checkerboard disturb pattern, was obtained after process optimization. Write endurance tests did not show degradation of the cell properties.

Keywords

copper; integrated circuit metallisation; integrated circuit yield; magnetoresistive devices; random-access storage; tunnel transistors; 0.18 micron; 128 KB; 2 kB; Cu; Cu metallization logic-based process; array test chip; cell properties; magnetic tunnel junction; magnetoresistive random access memory; nonvolatile memory; resistance distribution function; transistor; yield analysis; Degradation; Distribution functions; Fabrication; Magnetic analysis; Magnetic tunneling; Magnetoresistance; Metallization; Nonvolatile memory; Random access memory; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221063

Filename

1221063