High performance 35 nm gate CMOSFETs with vertical scaling and total stress control for 65 nm technology

Author

Goto, K. ; Tagawa, Y. ; Ohta, H. ; Morioka, H. ; Pidin, S. ; Momiyama, Y. ; Okabe, K. ; Kokura, H. ; Inagaki, S. ; Kikuchi, Y. ; Kase, M. ; Hashimoto, K. ; Kojima, M. ; Sugii, T.

Author_Institution

Fujitsu Ltd., Tokyo, Japan

fYear

2003

fDate

10-12 June 2003

Firstpage

49

Lastpage

50

Abstract

This paper demonstrates high performance 35 nm gate length CMOSFETs for 65 nm technology node. The impact of vertical gate scaling on dopant activation in poly-Si gate and device performance is investigated. Total stress controls form both STI and interconnect improved the nMOS drive current up to 5-10% without degradation for pMOS. Excellent controlled 35 nm gate length CMOSFETs are achieved with a high drive current of 650 uA/um for nMOS and 310 uA/um for pMOS at Ioff=70 nA/um at supply voltage of 0.85 V. Low CV/I values of 0.85 ps for nMOS and 1.61 ps for pMOS are obtained. These results are competitive among the latest published data.

Keywords

MOSFET; elemental semiconductors; isolation technology; nanotechnology; silicon; stress control; 0.85 ps; 1.61 ps; 35 nm; 65 nm; CMOSFETs; STI; degradation; device performance; dopant activation; drive current; nanotechnology node; poly Si gate; shallow trench isolation; stress control; vertical gate scaling; Annealing; CMOS technology; CMOSFETs; Capacitance; Electron beams; MOS devices; Semiconductor films; Silicides; Strain measurement; Stress control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221080

Filename

1221080