Ultra-low power and high speed SRAM for mobile applications using single Poly-Si gate 90 nm CMOS technology

Author

Koh, K. ; Hwang, B.J. ; Han, G.H. ; Kwak, K.H. ; Son, Y.S. ; Jang, J.H. ; Kim, H.S. ; Park, D. ; Kinam Kim

Author_Institution

R&D Center, Samsung Electron. Co. Ltd., Kyunggi-Do, South Korea

fYear

2003

fDate

10-12 June 2003

Firstpage

67

Lastpage

68

Abstract

High speed and ultra-low power SRAM using single gate CMOS technology was developed. The drive currents of NMOSFET and PMOSFET were 410 /spl mu/A//spl mu/m and 205 /spl mu/A//spl mu/m, respectively. The random access time of 17 ns at 1.65 V operation voltage was achieved for the first time in low power application by the reduction of loading capacitance. Standby current was less than 15 /spl mu/A/chip. The highly manufacturable compact cell of 0.84 /spl mu/m/sup 2/ area was integrated using PR (photo resist) flow technology and novel contact layout.

Keywords

CMOS memory circuits; MOSFET; SRAM chips; elemental semiconductors; photoresists; silicon; 1.65 V; 17 ns; 90 nm; CMOS technology; NMOSFET; PMOSFET; Si; drive currents; flow technology; high speed SRAM; loading capacitance; photoresist; random access time; single poly-Si gate; ultra low power SRAM; CMOS technology; Capacitance; Leakage current; Lithography; MOSFET circuits; Optical control; Random access memory; Read-write memory; Research and development; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221089

Filename

1221089