Integration of Cu/low-k dual-damascene interconnects with a porous PAE/SiOC hybrid structure for 65 nm-node high performance eDRAM

Porous PAE/SiOC(k2.5)/SiC(k3.5) hybrid dual damascene (DD) interconnects have been successfully integrated for a 65 nm-node high performance embedded DRAM. The hybrid DD structure was fabricated by applying a triple hard mask (THM) process-for the first time-that resulted in excellent yield of 1 M via chains. The THM process produces a well-controlled DD profile without complexity of process integration. The porosity of the porous PAE was optimized to enhance the mechanical strength and thus prevent process-induced damages. The hybrid DD interconnects with the porous PAE and the second-generation SiOC/SiC (k2.5/3.5) dielectrics resulted in no degradation of line-to-line leakage current and elimination of stress-induced voiding. It is concluded that this hybrid DD interconnects fabricated by the THM process is the most promising one to satisfy all the requirements for 65 nm-node eDRAM.