Impacts of high modulus ultra low-k/Cu 300 mm-wafer integration for 65 nm technology node and beyond

Author

Sone, S. ; Ohashi, N. ; Shin, H.J. ; Misawa, K. ; Kaji, N. ; Inukai, K. ; Matsushita, A. ; Sudou, K. ; Tokitoh, S. ; Kondo, S. ; Yoon, B.U. ; Yoneda, K. ; Yoshie, T. ; Ohtsuka, N. ; Okamura, H. ; Toyoda, Y. ; Shoji, F. ; Nasuno, T. ; Shimada, M. ; Ogawa,

Author_Institution

Res. Dept., Semicond. Leading Edge Technol. Inc., Tsukuba, Japan

fYear

2003

fDate

10-12 June 2003

Firstpage

125

Lastpage

126

Abstract

A robust low-k material (k<2.3)/Cu multilevel interconnects are integrated using optimized 300 mm-wafer processes for 65 nm node and beyond. Hybrid-structure low-k ILD of porous MSQ (k=2.3)/fluorinated-arylene (F.A., k=2.2) films reduces the effective k value (keff) to 2.6 and sh6ws good electrical characteristics. Improved mechanical properties of low-k materials (Modulus /spl sim/10 GPa) greatly increase a process compatibility with 300 mm-wafer manufacturing technology such as low pressure CMP and plasma treatments during low-k integration.

Keywords

Young´s modulus; chemical mechanical polishing; copper; hardness; integrated circuit interconnections; permittivity; plasma materials processing; polymer films; porous materials; 300 mm; 65 nm; Cu; Cu wafer integration; Youngs modulus; chemical mechanical polishing; dielectric integration; dielectric materials; electrical properties; fabrication technology; hybrid-structure; mechanical properties; multilevel interconnects; plasma treatments; process compatibility; Capacitance; Delamination; Electric resistance; Manufacturing processes; Mechanical factors; Plasma applications; Plasma properties; Polymers; Robustness; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221117

Filename

1221117