Parallel clock tree synthesis

Clock tree synthesis (CTS) is an important phase of the physical design of integrated circuits in which the network carrying the clock signal is laid out. As the sizes of modern circuits continue to grow exponentially, the amount of computation required in designing the clock network increases proportionally. CTS is a prime candidate for parallelization but is almost entirely unexplored in the literature. This paper highlights properties of common algorithms for performing CTS that are favorable for parallelization and presents parallel versions of the algorithms. Practical considerations in implementing parallel versions of the algorithms are also discussed. Experiments show the effectiveness of the parallel implementations in achieving linear speedup with the number of processors.