Events suppression technique for high performance VHDL simulation

The performance and efficiency of event driven simulations, such as VHDL and Verilog simulation, depend on the number of events that occur during the simulation. We classify events into two categories, sensitive events and insensitive events, according to the necessity of simulations, and also show a classification algorithm for both combinational logic circuits, and synchronous logic circuits and implement the optimization methodology that eliminates unnecessary simulations caused by the insensitive events. Five experiments show that optimized VHDL programs run about two times faster than the original ones