Design of a low leakage ESD clamp for high voltage supply in 65nm CMOS technology

Author

Parthasarathy, Srinivasan ; Salcedo, Javier A. ; Hajjar, Jean-Jacques

Author_Institution

Analog Devices, Inc., Wilmington, MA, USA

fYear

2014

fDate

1-5 June 2014

Abstract

System on Chip (SOC) designs in 65nm and beyond CMOS processes have the need to support higher voltage power supply domains in addition to the more traditional core and I/O voltages. In this work a new supply clamp architecture is proposed which ensures a reliable low leakage performance at the Higher supply voltages (5.0V for 65nm). The clamp´s turn-on characteristics spans the full duration of the actual ESD events making it fully capable to effectively protect the sensitive devices in the 5V core circuit. The low leakage aspect of the supply clamp is demonstrated with the help of high temperature measurements.

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit design; integrated circuit reliability; power supply circuits; system-on-chip; CMOS technology; high voltage supply; low leakage ESD clamp; reliable low leakage performance; size 65 nm; supply clamp architecture; system-on-chip designs; voltage 5 V; Clamps; Electrostatic discharges; Integrated circuit reliability; Logic gates; MOS devices; Transient analysis; 65nm and ESD; CDM; SOC;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 2014 IEEE International

Conference_Location

Waikoloa, HI

Type

conf

DOI

10.1109/IRPS.2014.6860654

Filename

6860654