Performance evaluation of CP-PACS on CG benchmark

Author

Itakura, Kenichi ; Nakamura, Hiroshi ; Boku, Taisuke ; Nakazawa, Kisaburo

Author_Institution

Inst. of Inf. Sci. & Electron., Tsukuba Univ., Ibaraki, Japan

fYear

1997

fDate

28 Apr-2 May 1997

Firstpage

678

Lastpage

683

Abstract

We evaluate NAS Parallel Benchmarks ver.1 Kernel CG on massively parallel processor CP-PACS, and analyze the results. CP-PACS´ CPU has a special register which is auto-incremented by clock cycle, and we can measure the time spent on any function routine with very high accuracy. As a result of the performance analysis, especially of the data transfer time, our desk-top estimation fits the measured results almost perfectly. From this analysis, we can show the program bottlenecks when executing with a large number of PUs

Keywords

distributed memory systems; parallel machines; parallel programming; performance evaluation; software performance evaluation; CG benchmark; CP-PACS; CPU; NAS Parallel Benchmarks; data transfer time; desk-top estimation; massively parallel processor; performance evaluation; program bottlenecks; time measurement; Central Processing Unit; Character generation; Clocks; Delay; Instruments; Large-scale systems; Performance analysis; Pipeline processing; Reduced instruction set computing; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Computing on the Information Superhighway, 1997. HPC Asia '97

Conference_Location

Seoul

Print_ISBN

0-8186-7901-8

Type

conf

DOI

10.1109/HPC.1997.592230

Filename

592230