HV PMOSFET VT shift suppression after HTOL by modified p-Hump prevention ion implant

Generally, LCD(liquid crystal display) driver IC(integrated circuit) requires high voltage of more than 10V and adopts MTI(middle trench isolation) scheme which is deeply trenched to get isolation characteristics on the high voltage according to chip shrinkage. The Vth(Threshold Voltage) shift of HV devices after HTOL(high temperature operating life time) becomes much more serious hazard for product reliability. HV p-channel MOSFET(PMOS) with trench isolation scheme are especially sensitive to these Vth shift issues caused by HEIP. It was found that electron trapping at interface between sidewall oxide and nitride liner in middle trench isolation(MTI) induces channel shorting due to punch through by lowering Vth at the corner of transistor, thereby resulting in the leakage current. This leakage current increment caused by Vth shift makes logic function fail. In this paper, we propose the optimized sidewall thickness and the effectiveness of additional ion implant process which have strong resistance against hot electron induced punch through regarding that offset leakage current is increased after HTOL(high temperature operating lifetime) stressing test for devices prepared with MTI processing scheme.