Three-pattern tests for delay faults

To improve the quality of CMOS digital circuits, more complex fault models than single stuck-at have been proposed. This paper focuses on the effect of inaccurate delay modeling on delay fault testing. It is shown that accurate delay models are needed for effective delay fault testing. This is particularly important for large timing optimized circuits with many paths. Limitations of the path delay fault model are shown, and even the assumption that 2-pattern tests are sufficient for delay testing is shown to have limitations