DocumentCode
1871623
Title
Speeding up behavioral test pattern generation using an algorithmic improvement
Author
Vandeventer, L. ; Santucci, J.-F. ; Giambiasi, N.
Author_Institution
Lab. d´´Etudes et de Recherche en Informatique, EERIE, Nimes, France
fYear
1994
fDate
25-28 Apr 1994
Firstpage
226
Lastpage
231
Abstract
In this paper, we focus on an improvement of test pattern generation for circuit descriptions written in hardware description languages according to their behavior. The improvement method stems from the “headlines” defined at the gate level by structural test approaches. The improvement method is implemented and inserted in a behavioral test pattern generator in order to be validated. Experimental results have been obtained which show the efficiency of our approach
Keywords
automatic testing; digital integrated circuits; integrated circuit testing; logic testing; specification languages; HDL; algorithmic improvement; behavioral test pattern generation; circuit descriptions; gate level; hardware description languages; headlines; structural test approaches; Acceleration; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit testing; Decision trees; Equations; Hardware design languages; Heuristic algorithms; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1994. Proceedings., 12th IEEE
Conference_Location
Cherry Hill, NJ
Print_ISBN
0-8186-5440-6
Type
conf
DOI
10.1109/VTEST.1994.292308
Filename
292308
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