• DocumentCode
    1872325
  • Title

    Delay-fault testability preservation of the concurrent decomposition and factorization transformations

  • Author

    El-Maleh, Aiman ; Rajski, Janusz

  • Author_Institution
    MACS Lab., McGill Univ., Montreal, Que., Canada
  • fYear
    1994
  • fDate
    25-28 Apr 1994
  • Firstpage
    15
  • Lastpage
    21
  • Abstract
    Recently, a new, very efficient method of multilevel logic synthesis based on factorization and decomposition of Boolean expressions has been introduced. It has been shown that the transformations used by this method preserve the single stuck-at testability of two-level circuits. This paper shows that single-cube extraction, double-cube extraction, and dual-extraction of double-cubes∈D1,1,2 and D2,2,2 preserve testability with respect to a general robust path-delay-fault (RPDF) test set. However, the authors show that while dual-extraction of double-cubes∈D2,2,3 preserves RPDF testability of paths through the extracted divisors with respect to a single-input-changing test set, it does not guarantee RPDF testability preservation of unmodified paths. Furthermore, the authors provide sufficient conditions for algebraic resubstitution with complement to preserve RPDF testability that cover a larger class of complementary expressions than was known previously. The testability preservation of these transformations is demonstrated on a set of RPDF testable Berkeley PLAs
  • Keywords
    Boolean functions; logic CAD; logic arrays; logic testing; many-valued logics; Berkeley PLAs; Boolean expressions; algebraic resubstitution; concurrent decomposition transformations; concurrent factorization transformations; delay-fault testability; double-cube extraction; dual-extraction; multilevel logic synthesis; robust path-delay-fault; single stuck-at testability; single-cube extraction; single-input-changing test set; Boolean functions; Circuit faults; Circuit synthesis; Circuit testing; Delay; Integrated circuit modeling; Laboratories; Logic testing; Network synthesis; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1994. Proceedings., 12th IEEE
  • Conference_Location
    Cherry Hill, NJ
  • Print_ISBN
    0-8186-5440-6
  • Type

    conf

  • DOI
    10.1109/VTEST.1994.292340
  • Filename
    292340